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authorGravatar Ningsheng Jian <njian@openjdk.org> 2021-03-25 01:57:03 +0000
committerGravatar Ningsheng Jian <njian@openjdk.org> 2021-03-25 01:57:03 +0000
commit3e18330a33386f48e691d358a73521e23ef0618d (patch)
tree3931dfeb1d6440a0ec3b40940d48bea07643dc56
parent0ff81682e63fe2964fee7149b70baa299169894a (diff)
downloadjdk-3e18330a33386f48e691d358a73521e23ef0618d.tar.gz
jdk-3e18330a33386f48e691d358a73521e23ef0618d.zip
8264018: AArch64: NEON loadV2 and storeV2 addressing is wrong
Reviewed-by: adinn, aph
-rw-r--r--src/hotspot/cpu/aarch64/aarch64.ad1
-rw-r--r--src/hotspot/cpu/aarch64/aarch64_neon.ad136
-rw-r--r--src/hotspot/cpu/aarch64/aarch64_neon_ad.m415
3 files changed, 76 insertions, 76 deletions
diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad
index ab17c938b30..7cc74e38bbc 100644
--- a/src/hotspot/cpu/aarch64/aarch64.ad
+++ b/src/hotspot/cpu/aarch64/aarch64.ad
@@ -6260,6 +6260,7 @@ operand iRegL2I(iRegL reg) %{
interface(REG_INTER)
%}
+opclass vmem2(indirect, indIndex, indOffI2, indOffL2);
opclass vmem4(indirect, indIndex, indOffI4, indOffL4);
opclass vmem8(indirect, indIndex, indOffI8, indOffL8);
opclass vmem16(indirect, indIndex, indOffI16, indOffL16);
diff --git a/src/hotspot/cpu/aarch64/aarch64_neon.ad b/src/hotspot/cpu/aarch64/aarch64_neon.ad
index 59aa45c2de1..bd8f2ac0c77 100644
--- a/src/hotspot/cpu/aarch64/aarch64_neon.ad
+++ b/src/hotspot/cpu/aarch64/aarch64_neon.ad
@@ -31,7 +31,7 @@
// ------------------------------ Load/store/reinterpret -----------------------
// Load Vector (16 bits)
-instruct loadV2(vecD dst, memory mem)
+instruct loadV2(vecD dst, vmem2 mem)
%{
predicate(n->as_LoadVector()->memory_size() == 2);
match(Set dst (LoadVector mem));
@@ -41,8 +41,41 @@ instruct loadV2(vecD dst, memory mem)
ins_pipe(vload_reg_mem64);
%}
+// Load Vector (32 bits)
+instruct loadV4(vecD dst, vmem4 mem)
+%{
+ predicate(n->as_LoadVector()->memory_size() == 4);
+ match(Set dst (LoadVector mem));
+ ins_cost(4 * INSN_COST);
+ format %{ "ldrs $dst,$mem\t# vector (32 bits)" %}
+ ins_encode( aarch64_enc_ldrvS(dst, mem) );
+ ins_pipe(vload_reg_mem64);
+%}
+
+// Load Vector (64 bits)
+instruct loadV8(vecD dst, vmem8 mem)
+%{
+ predicate(n->as_LoadVector()->memory_size() == 8);
+ match(Set dst (LoadVector mem));
+ ins_cost(4 * INSN_COST);
+ format %{ "ldrd $dst,$mem\t# vector (64 bits)" %}
+ ins_encode( aarch64_enc_ldrvD(dst, mem) );
+ ins_pipe(vload_reg_mem64);
+%}
+
+// Load Vector (128 bits)
+instruct loadV16(vecX dst, vmem16 mem)
+%{
+ predicate(UseSVE == 0 && n->as_LoadVector()->memory_size() == 16);
+ match(Set dst (LoadVector mem));
+ ins_cost(4 * INSN_COST);
+ format %{ "ldrq $dst,$mem\t# vector (128 bits)" %}
+ ins_encode( aarch64_enc_ldrvQ(dst, mem) );
+ ins_pipe(vload_reg_mem128);
+%}
+
// Store Vector (16 bits)
-instruct storeV2(vecD src, memory mem)
+instruct storeV2(vecD src, vmem2 mem)
%{
predicate(n->as_StoreVector()->memory_size() == 2);
match(Set mem (StoreVector mem src));
@@ -52,6 +85,39 @@ instruct storeV2(vecD src, memory mem)
ins_pipe(vstore_reg_mem64);
%}
+// Store Vector (32 bits)
+instruct storeV4(vecD src, vmem4 mem)
+%{
+ predicate(n->as_StoreVector()->memory_size() == 4);
+ match(Set mem (StoreVector mem src));
+ ins_cost(4 * INSN_COST);
+ format %{ "strs $mem,$src\t# vector (32 bits)" %}
+ ins_encode( aarch64_enc_strvS(src, mem) );
+ ins_pipe(vstore_reg_mem64);
+%}
+
+// Store Vector (64 bits)
+instruct storeV8(vecD src, vmem8 mem)
+%{
+ predicate(n->as_StoreVector()->memory_size() == 8);
+ match(Set mem (StoreVector mem src));
+ ins_cost(4 * INSN_COST);
+ format %{ "strd $mem,$src\t# vector (64 bits)" %}
+ ins_encode( aarch64_enc_strvD(src, mem) );
+ ins_pipe(vstore_reg_mem64);
+%}
+
+// Store Vector (128 bits)
+instruct storeV16(vecX src, vmem16 mem)
+%{
+ predicate(n->as_StoreVector()->memory_size() == 16);
+ match(Set mem (StoreVector mem src));
+ ins_cost(4 * INSN_COST);
+ format %{ "strq $mem,$src\t# vector (128 bits)" %}
+ ins_encode( aarch64_enc_strvQ(src, mem) );
+ ins_pipe(vstore_reg_mem128);
+%}
+
instruct reinterpretD(vecD dst)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
@@ -3703,72 +3769,6 @@ instruct vabd2D(vecX dst, vecX src1, vecX src2)
ins_pipe(vunop_fp128);
%}
-// Load Vector (32 bits)
-instruct loadV4(vecD dst, vmem4 mem)
-%{
- predicate(n->as_LoadVector()->memory_size() == 4);
- match(Set dst (LoadVector mem));
- ins_cost(4 * INSN_COST);
- format %{ "ldrs $dst,$mem\t# vector (32 bits)" %}
- ins_encode( aarch64_enc_ldrvS(dst, mem) );
- ins_pipe(vload_reg_mem64);
-%}
-
-// Load Vector (64 bits)
-instruct loadV8(vecD dst, vmem8 mem)
-%{
- predicate(n->as_LoadVector()->memory_size() == 8);
- match(Set dst (LoadVector mem));
- ins_cost(4 * INSN_COST);
- format %{ "ldrd $dst,$mem\t# vector (64 bits)" %}
- ins_encode( aarch64_enc_ldrvD(dst, mem) );
- ins_pipe(vload_reg_mem64);
-%}
-
-// Load Vector (128 bits)
-instruct loadV16(vecX dst, vmem16 mem)
-%{
- predicate(UseSVE == 0 && n->as_LoadVector()->memory_size() == 16);
- match(Set dst (LoadVector mem));
- ins_cost(4 * INSN_COST);
- format %{ "ldrq $dst,$mem\t# vector (128 bits)" %}
- ins_encode( aarch64_enc_ldrvQ(dst, mem) );
- ins_pipe(vload_reg_mem128);
-%}
-
-// Store Vector (32 bits)
-instruct storeV4(vecD src, vmem4 mem)
-%{
- predicate(n->as_StoreVector()->memory_size() == 4);
- match(Set mem (StoreVector mem src));
- ins_cost(4 * INSN_COST);
- format %{ "strs $mem,$src\t# vector (32 bits)" %}
- ins_encode( aarch64_enc_strvS(src, mem) );
- ins_pipe(vstore_reg_mem64);
-%}
-
-// Store Vector (64 bits)
-instruct storeV8(vecD src, vmem8 mem)
-%{
- predicate(n->as_StoreVector()->memory_size() == 8);
- match(Set mem (StoreVector mem src));
- ins_cost(4 * INSN_COST);
- format %{ "strd $mem,$src\t# vector (64 bits)" %}
- ins_encode( aarch64_enc_strvD(src, mem) );
- ins_pipe(vstore_reg_mem64);
-%}
-
-// Store Vector (128 bits)
-instruct storeV16(vecX src, vmem16 mem)
-%{
- predicate(n->as_StoreVector()->memory_size() == 16);
- match(Set mem (StoreVector mem src));
- ins_cost(4 * INSN_COST);
- format %{ "strq $mem,$src\t# vector (128 bits)" %}
- ins_encode( aarch64_enc_strvQ(src, mem) );
- ins_pipe(vstore_reg_mem128);
-%}
-
instruct replicate8B(vecD dst, iRegIorL2I src)
%{
predicate(n->as_Vector()->length() == 4 ||
diff --git a/src/hotspot/cpu/aarch64/aarch64_neon_ad.m4 b/src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
index 0918114ff76..49292476549 100644
--- a/src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
+++ b/src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
@@ -59,7 +59,7 @@ dnl
// ------------------------------ Load/store/reinterpret -----------------------
define(`VLoadStore', `
// ifelse(load, $3, Load, Store) Vector ($6 bits)
-instruct $3V$4`'(vec$5 $7, ifelse($4, 2, memory, vmem$4) mem)
+instruct $3V$4`'(vec$5 $7, vmem$4 mem)
%{
predicate($8`n->as_'ifelse(load, $3, Load, Store)Vector()->memory_size() == $4);
match(Set ifelse(load, $3, dst (LoadVector mem), mem (StoreVector mem src)));
@@ -70,7 +70,13 @@ instruct $3V$4`'(vec$5 $7, ifelse($4, 2, memory, vmem$4) mem)
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8
VLoadStore(ldrh, H, load, 2, D, 16, dst, )
+VLoadStore(ldrs, S, load, 4, D, 32, dst, )
+VLoadStore(ldrd, D, load, 8, D, 64, dst, )
+VLoadStore(ldrq, Q, load, 16, X, 128, dst, UseSVE == 0 && )
VLoadStore(strh, H, store, 2, D, 16, src, )
+VLoadStore(strs, S, store, 4, D, 32, src, )
+VLoadStore(strd, D, store, 8, D, 64, src, )
+VLoadStore(strq, Q, store, 16, X, 128, src, )
dnl
define(`REINTERPRET', `
instruct reinterpret$1`'(vec$1 dst)
@@ -1499,13 +1505,6 @@ VFABD(fabd, fabd, 2, F, D, S, 64)
VFABD(fabd, fabd, 4, F, X, S, 128)
VFABD(fabd, fabd, 2, D, X, D, 128)
dnl
-VLoadStore(ldrs, S, load, 4, D, 32, dst, )
-VLoadStore(ldrd, D, load, 8, D, 64, dst, )
-VLoadStore(ldrq, Q, load, 16, X, 128, dst, UseSVE == 0 && )
-VLoadStore(strs, S, store, 4, D, 32, src, )
-VLoadStore(strd, D, store, 8, D, 64, src, )
-VLoadStore(strq, Q, store, 16, X, 128, src, )
-dnl
define(`VREPLICATE', `
instruct replicate$3$4$5`'(vec$6 dst, $7 ifelse($7, immI0, zero, $7, immI, con, src))
%{